moved a bunch of garbage (things that have nothing to do in root) to _trash
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# Copyright (c) 2014-2024, Emmanuel Blot <emmanuel.blot@free.fr>
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# Copyright (c) 2016, Emmanuel Bouaziz <ebouaziz@free.fr>
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# All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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"""GPIO/BitBang support for PyFdti"""
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from struct import calcsize as scalc, unpack as sunpack
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from typing import Iterable, Optional, Tuple, Union
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from .ftdi import Ftdi, FtdiError
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from .misc import is_iterable
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class GpioException(FtdiError):
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"""Base class for GPIO errors.
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"""
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class GpioPort:
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"""Duck-type GPIO port for GPIO all controllers.
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"""
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class GpioBaseController(GpioPort):
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"""GPIO controller for an FTDI port, in bit-bang legacy mode.
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GPIO bit-bang mode is limited to the 8 lower pins of each GPIO port.
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"""
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def __init__(self):
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self._ftdi = Ftdi()
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self._direction = 0
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self._width = 0
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self._mask = 0
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self._frequency = 0
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@property
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def ftdi(self) -> Ftdi:
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"""Return the Ftdi instance.
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:return: the Ftdi instance
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"""
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return self._ftdi
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@property
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def is_connected(self) -> bool:
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"""Reports whether a connection exists with the FTDI interface.
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:return: the FTDI slave connection status
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"""
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return self._ftdi.is_connected
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def configure(self, url: str, direction: int = 0,
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**kwargs) -> int:
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"""Open a new interface to the specified FTDI device in bitbang mode.
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:param str url: a FTDI URL selector
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:param int direction: a bitfield specifying the FTDI GPIO direction,
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where high level defines an output, and low level defines an
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input
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:param initial: optional initial GPIO output value
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:param pace: optional pace in GPIO sample per second
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:return: actual bitbang pace in sample per second
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"""
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if self.is_connected:
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raise FtdiError('Already connected')
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kwargs = dict(kwargs)
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frequency = kwargs.get('frequency', None)
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if frequency is None:
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frequency = kwargs.get('baudrate', None)
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for k in ('direction', 'sync', 'frequency', 'baudrate'):
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if k in kwargs:
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del kwargs[k]
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self._frequency = self._configure(url, direction, frequency, **kwargs)
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def close(self, freeze: bool = False) -> None:
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"""Close the GPIO port.
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:param freeze: if set, FTDI port is not reset to its default
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state on close. This means the port is left with
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its current configuration and output signals.
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This feature should not be used except for very
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specific needs.
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"""
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if self._ftdi.is_connected:
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self._ftdi.close(freeze)
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def get_gpio(self) -> GpioPort:
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"""Retrieve the GPIO port.
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This method is mostly useless, it is a wrapper to duck type other
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GPIO APIs (I2C, SPI, ...)
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:return: GPIO port
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"""
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return self
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@property
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def direction(self) -> int:
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"""Reports the GPIO direction.
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:return: a bitfield specifying the FTDI GPIO direction, where high
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level reports an output pin, and low level reports an input pin
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"""
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return self._direction
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@property
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def pins(self) -> int:
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"""Report the configured GPIOs as a bitfield.
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A true bit represents a GPIO, a false bit a reserved or not
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configured pin.
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:return: always 0xFF for GpioController instance.
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"""
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return self._mask
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@property
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def all_pins(self) -> int:
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"""Report the addressable GPIOs as a bitfield.
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A true bit represents a pin which may be used as a GPIO, a false bit
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a reserved pin
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:return: always 0xFF for GpioController instance.
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"""
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return self._mask
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@property
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def width(self) -> int:
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"""Report the FTDI count of addressable pins.
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:return: the width of the GPIO port.
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"""
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return self._width
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@property
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def frequency(self) -> float:
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"""Return the pace at which sequence of GPIO samples are read
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and written.
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"""
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return self._frequency
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def set_frequency(self, frequency: Union[int, float]) -> None:
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"""Set the frequency at which sequence of GPIO samples are read
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and written.
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:param frequency: the new frequency, in GPIO samples per second
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"""
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raise NotImplementedError('GpioBaseController cannot be instanciated')
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def set_direction(self, pins: int, direction: int) -> None:
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"""Update the GPIO pin direction.
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:param pins: which GPIO pins should be reconfigured
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:param direction: a bitfield of GPIO pins. Each bit represent a
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GPIO pin, where a high level sets the pin as output and a low
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level sets the pin as input/high-Z.
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"""
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if direction > self._mask:
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raise GpioException("Invalid direction mask")
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self._direction &= ~pins
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self._direction |= (pins & direction)
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self._update_direction()
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def _configure(self, url: str, direction: int,
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frequency: Union[int, float, None] = None, **kwargs) -> int:
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raise NotImplementedError('GpioBaseController cannot be instanciated')
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def _update_direction(self) -> None:
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raise NotImplementedError('Missing implementation')
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class GpioAsyncController(GpioBaseController):
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"""GPIO controller for an FTDI port, in bit-bang asynchronous mode.
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GPIO accessible pins are limited to the 8 lower pins of each GPIO port.
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Asynchronous bitbang output are updated on write request using the
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:py:meth:`write` method, clocked at the selected frequency.
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Asynchronous bitbang input are sampled at the same rate, as soon as the
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controller is initialized. The GPIO input samples fill in the FTDI HW
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buffer until it is filled up, in which case sampling stops until the
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GPIO samples are read out with the :py:meth:`read` method. It may be
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therefore hard to use, except if peek mode is selected,
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see :py:meth:`read` for details.
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Note that FTDI internal clock divider cannot generate any arbitrary
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frequency, so the closest frequency to the request one that can be
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generated is selected. The actual :py:attr:`frequency` may be tested to
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check if it matches the board requirements.
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"""
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def read(self, readlen: int = 1, peek: Optional[bool] = None,
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noflush: bool = False) -> Union[int, bytes]:
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"""Read the GPIO input pin electrical level.
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:param readlen: how many GPIO samples to retrieve. Each sample is
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8-bit wide.
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:param peek: whether to peek/sample the instantaneous GPIO pin
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values from port, or to use the HW FIFO. The HW FIFO is
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continously filled up with GPIO sample at the current
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frequency, until it is full - samples are no longer
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collected until the FIFO is read. This means than
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non-peek mode read "old" values, with no way to know at
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which time they have been sampled. PyFtdi ensures that
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old sampled values before the completion of a previous
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GPIO write are discarded. When peek mode is selected,
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readlen should be 1.
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:param noflush: whether to disable the RX buffer flush before
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reading out data
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:return: a 8-bit wide integer if peek mode is used, or
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a bytes buffer otherwise.
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"""
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if not self.is_connected:
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raise GpioException('Not connected')
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if peek is None and readlen == 1:
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# compatibility with legacy API
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peek = True
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if peek:
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if readlen != 1:
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raise ValueError('Invalid read length with peek mode')
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return self._ftdi.read_pins()
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# in asynchronous bitbang mode, the FTDI-to-host FIFO is filled in
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# continuously once this mode is activated. This means there is no
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# way to trigger the exact moment where the buffer is filled in, nor
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# to define the write pointer in the buffer. Reading out this buffer
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# at any time is likely to contain a mix of old and new values.
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# Anyway, flushing the FTDI-to-host buffer seems to be a proper
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# to get in sync with the buffer.
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if noflush:
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return self._ftdi.read_data(readlen)
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loop = 10000
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while loop:
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loop -= 1
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# do not attempt to do anything till the FTDI HW buffer has been
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# emptied, i.e. previous write calls have been handled.
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status = self._ftdi.poll_modem_status()
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if status & Ftdi.MODEM_TEMT:
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# TX buffer is now empty, any "write" GPIO rquest has completed
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# so start reading GPIO samples from this very moment.
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break
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else:
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# sanity check to avoid endless loop on errors
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raise FtdiError('FTDI TX buffer error')
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# now flush the FTDI-to-host buffer as it keeps being filled with data
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self._ftdi.purge_tx_buffer()
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# finally perform the actual read out
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return self._ftdi.read_data(readlen)
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def write(self, out: Union[bytes, bytearray, int]) -> None:
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"""Set the GPIO output pin electrical level, or output a sequence of
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bytes @ constant frequency to GPIO output pins.
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:param out: a bitfield of GPIO pins, or a sequence of them
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"""
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if not self.is_connected:
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raise GpioException('Not connected')
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if isinstance(out, (bytes, bytearray)):
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pass
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else:
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if isinstance(out, int):
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out = bytes([out])
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else:
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if not is_iterable(out):
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raise TypeError('Invalid output value')
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for val in out:
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if val > self._mask:
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raise ValueError('Invalid output value')
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out = bytes(out)
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self._ftdi.write_data(out)
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def set_frequency(self, frequency: Union[int, float]) -> None:
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"""Set the frequency at which sequence of GPIO samples are read
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and written.
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note: FTDI may update its clock register before it has emptied its
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internal buffer. If the current frequency is "low", some
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yet-to-output bytes may end up being clocked at the new frequency.
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Unfortunately, it seems there is no way to wait for the internal
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buffer to be emptied out. They can be flushed (i.e. discarded), but
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not synchronized :-(
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PyFtdi client should add "some" short delay to ensure a previous,
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long write request has been fully output @ low freq before changing
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the frequency.
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Beware that only some exact frequencies can be generated. Contrary
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to the UART mode, an approximate frequency is always accepted for
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GPIO/bitbang mode. To get the actual frequency, and optionally abort
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if it is out-of-spec, use :py:meth:`frequency` property.
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:param frequency: the new frequency, in GPIO samples per second
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"""
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self._frequency = float(self._ftdi.set_baudrate(int(frequency), False))
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def _configure(self, url: str, direction: int,
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frequency: Union[int, float, None] = None, **kwargs) -> int:
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if 'initial' in kwargs:
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initial = kwargs['initial']
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del kwargs['initial']
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else:
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initial = None
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if 'debug' in kwargs:
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# debug is not implemented
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del kwargs['debug']
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baudrate = int(frequency) if frequency is not None else None
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baudrate = self._ftdi.open_bitbang_from_url(url,
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direction=direction,
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sync=False,
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baudrate=baudrate,
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**kwargs)
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self._width = 8
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self._mask = (1 << self._width) - 1
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self._direction = direction & self._mask
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if initial is not None:
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initial &= self._mask
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self.write(initial)
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return float(baudrate)
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def _update_direction(self) -> None:
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self._ftdi.set_bitmode(self._direction, Ftdi.BitMode.BITBANG)
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# old API names
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open_from_url = GpioBaseController.configure
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read_port = read
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write_port = write
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# old API compatibility
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GpioController = GpioAsyncController
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class GpioSyncController(GpioBaseController):
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"""GPIO controller for an FTDI port, in bit-bang synchronous mode.
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GPIO accessible pins are limited to the 8 lower pins of each GPIO port.
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Synchronous bitbang input and output are synchronized. Eveery time GPIO
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output is updated, the GPIO input is sampled and buffered.
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Update and sampling are clocked at the selected frequency. The GPIO
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samples are transfer in both direction with the :py:meth:`exchange`
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method, which therefore always returns as many input samples as output
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bytes.
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Note that FTDI internal clock divider cannot generate any arbitrary
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frequency, so the closest frequency to the request one that can be
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generated is selected. The actual :py:attr:`frequency` may be tested to
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check if it matches the board requirements.
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"""
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def exchange(self, out: Union[bytes, bytearray]) -> bytes:
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"""Set the GPIO output pin electrical level, or output a sequence of
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bytes @ constant frequency to GPIO output pins.
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:param out: the byte buffer to output as GPIO
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:return: a byte buffer of the same length as out buffer.
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"""
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if not self.is_connected:
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raise GpioException('Not connected')
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if isinstance(out, (bytes, bytearray)):
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pass
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else:
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if isinstance(out, int):
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out = bytes([out])
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elif not is_iterable(out):
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raise TypeError('Invalid output value')
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for val in out:
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if val > self._mask:
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raise GpioException("Invalid value")
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self._ftdi.write_data(out)
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data = self._ftdi.read_data_bytes(len(out), 4)
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return data
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def set_frequency(self, frequency: Union[int, float]) -> None:
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"""Set the frequency at which sequence of GPIO samples are read
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and written.
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:param frequency: the new frequency, in GPIO samples per second
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"""
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self._frequency = float(self._ftdi.set_baudrate(int(frequency), False))
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def _configure(self, url: str, direction: int,
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frequency: Union[int, float, None] = None, **kwargs):
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if 'initial' in kwargs:
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initial = kwargs['initial']
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del kwargs['initial']
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else:
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initial = None
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if 'debug' in kwargs:
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# debug is not implemented
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del kwargs['debug']
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baudrate = int(frequency) if frequency is not None else None
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baudrate = self._ftdi.open_bitbang_from_url(url,
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direction=direction,
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sync=True,
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baudrate=baudrate,
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**kwargs)
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self._width = 8
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self._mask = (1 << self._width) - 1
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self._direction = direction & self._mask
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if initial is not None:
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initial &= self._mask
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self.exchange(initial)
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return float(baudrate)
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def _update_direction(self) -> None:
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self._ftdi.set_bitmode(self._direction, Ftdi.BitMode.SYNCBB)
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class GpioMpsseController(GpioBaseController):
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"""GPIO controller for an FTDI port, in MPSSE mode.
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All GPIO pins are reachable, but MPSSE mode is slower than other modes.
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Beware that LSBs (b0..b7) and MSBs (b8..b15) are accessed with two
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subsequence commands, so a slight delay may occur when sampling or
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changing both groups at once. In other word, it is not possible to
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atomically read to / write from LSBs and MSBs. This might be worth
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checking the board design if atomic access to several lines is required.
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"""
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MPSSE_PAYLOAD_MAX_LENGTH = 0xFF00 # 16 bits max (- spare for control)
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def read(self, readlen: int = 1, peek: Optional[bool] = None) \
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-> Union[int, bytes, Tuple[int]]:
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"""Read the GPIO input pin electrical level.
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:param readlen: how many GPIO samples to retrieve. Each sample if
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:py:meth:`width` bit wide.
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:param peek: whether to peak current value from port, or to use
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MPSSE stream and HW FIFO. When peek mode is selected,
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readlen should be 1. It is not available with wide
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ports if some of the MSB pins are configured as input
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:return: a :py:meth:`width` bit wide integer if direct mode is used,
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a bytes buffer if :py:meth:`width` is a byte,
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a list of integer otherwise (MPSSE mode only).
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"""
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if not self.is_connected:
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raise GpioException('Not connected')
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if peek:
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if readlen != 1:
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raise ValueError('Invalid read length with direct mode')
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if self._width > 8:
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if (0xFFFF & ~self._direction) >> 8:
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raise ValueError('Peek mode not available with selected '
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'input config')
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if peek:
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return self._ftdi.read_pins()
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return self._read_mpsse(readlen)
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def write(self, out: Union[bytes, bytearray, Iterable[int], int]) -> None:
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"""Set the GPIO output pin electrical level, or output a sequence of
|
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bytes @ constant frequency to GPIO output pins.
|
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|
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:param out: a bitfield of GPIO pins, or a sequence of them
|
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"""
|
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if not self.is_connected:
|
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raise GpioException('Not connected')
|
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if isinstance(out, (bytes, bytearray)):
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pass
|
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else:
|
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if isinstance(out, int):
|
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out = [out]
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elif not is_iterable(out):
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raise TypeError('Invalid output value')
|
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for val in out:
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if val > self._mask:
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raise GpioException("Invalid value")
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self._write_mpsse(out)
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def set_frequency(self, frequency: Union[int, float]) -> None:
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if not self.is_connected:
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raise GpioException('Not connected')
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self._frequency = self._ftdi.set_frequency(float(frequency))
|
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def _update_direction(self) -> None:
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||||
# nothing to do in MPSSE mode, as direction is updated with each
|
||||
# GPIO command
|
||||
pass
|
||||
|
||||
def _configure(self, url: str, direction: int,
|
||||
frequency: Union[int, float, None] = None, **kwargs):
|
||||
frequency = self._ftdi.open_mpsse_from_url(url,
|
||||
direction=direction,
|
||||
frequency=frequency,
|
||||
**kwargs)
|
||||
self._width = self._ftdi.port_width
|
||||
self._mask = (1 << self._width) - 1
|
||||
self._direction = direction & self._mask
|
||||
return frequency
|
||||
|
||||
def _read_mpsse(self, count: int) -> Tuple[int]:
|
||||
if self._width > 8:
|
||||
cmd = bytearray([Ftdi.GET_BITS_LOW, Ftdi.GET_BITS_HIGH] * count)
|
||||
fmt = f'<{count}H'
|
||||
else:
|
||||
cmd = bytearray([Ftdi.GET_BITS_LOW] * count)
|
||||
fmt = None
|
||||
cmd.append(Ftdi.SEND_IMMEDIATE)
|
||||
if len(cmd) > self.MPSSE_PAYLOAD_MAX_LENGTH:
|
||||
raise ValueError('Too many samples')
|
||||
self._ftdi.write_data(cmd)
|
||||
size = scalc(fmt) if fmt else count
|
||||
data = self._ftdi.read_data_bytes(size, 4)
|
||||
if len(data) != size:
|
||||
raise FtdiError(f'Cannot read GPIO, recv {len(data)} '
|
||||
f'out of {size} bytes')
|
||||
if fmt:
|
||||
return sunpack(fmt, data)
|
||||
return data
|
||||
|
||||
def _write_mpsse(self,
|
||||
out: Union[bytes, bytearray, Iterable[int], int]) -> None:
|
||||
cmd = []
|
||||
low_dir = self._direction & 0xFF
|
||||
if self._width > 8:
|
||||
high_dir = (self._direction >> 8) & 0xFF
|
||||
for data in out:
|
||||
low_data = data & 0xFF
|
||||
high_data = (data >> 8) & 0xFF
|
||||
cmd.extend([Ftdi.SET_BITS_LOW, low_data, low_dir,
|
||||
Ftdi.SET_BITS_HIGH, high_data, high_dir])
|
||||
else:
|
||||
for data in out:
|
||||
cmd.extend([Ftdi.SET_BITS_LOW, data, low_dir])
|
||||
self._ftdi.write_data(bytes(cmd))
|
||||
Loading…
Add table
Add a link
Reference in a new issue